Averant Announces New Engine, Next Generation Testbench-less Bug Hunting, Support for System Verilog
Hayward, Calif. - June 5, 2008 - Averant Inc., a leading provider of advanced verification technology for RTL designs, today announces the development of significant new technologies, continuing its First In Formal leadership in formal property verification.
New Verification Engine: Maximizing the number of conclusive passes remains a goal of formal verification. Averant has developed a new engine based on proprietary algorithms capable of proving some previously unproven properties. This engine is seamlessly integrated in Averant's guided-proof system environment.
Next Generation Testbench-less Bug Hunting: To find deep bugs, Averant pioneered testbench-less bug hunting last year. Next generation testbench-less bug hunting improves the quality and speed of first generation algorithms, reaching more of the design space in significantly less time.
System Verilog Design Support: System Verilog Design (SVD) constructs support higher level specification of designs, and may become more widely used in the future.
"Averant's engines have been the leaders in the industry for
many years now" commented Ramin Hojati, president of Averant.
"We continue to build on our strength while improving
usability and design flow support".
The new engine is available now. Most of SVD constructs are available now, with the rest becoming available over the summer. Much of next generation bug hunting is available now, but some features will be coming later in the summer.
Averant Inc. is a privately held EDA firm specializing in formal verification of digital designs. Averant's signature product is Solidify, a robust platform for property, protocol, and automatic design checks - all without the need for simulators or test vectors. Averant's tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, visit http://www.averant.com.For inquiries:
Aug 17, 2021