From Averant comes an efficient arsenal of rigorous and comprehensive verification tools meant to help designers with today's complex designs:
At the heart of Averant's suite is Solidify, a high-performance formal verification engine with over 10 years of service in production. Solidify provides property verification, multiple internally developed engines, code coverage, testbenchless bug hunting, hierarchical verification, customizable engine coordination, simulation monitors and testbenches, plus source code debug tracing and waveforms and much more.
SolidSEC checks the functional equivalency between a design and a version with sequential modifications such as power optimizations. Additionally it integrates into Solidify to remove sequential redundancies, thus improving verification performance. It includes a combinational logic verifier.
SolidAC automatically checks a circuit for a number of common design problems. Reading only the design source, and with very little input from the user, SolidAC tracks down such problems as clock domain crossing problems, deadlock, deadcode, and a host of common but elusive design problems.
SolidTC employs formal technology to verify the correctness of false-path and multi-path constraints in a timing exceptions file (SDC).